(1) Field of the Invention
This invention relates to a method and pattern for routing power and ground for an integrated circuit chip.
(2) Description of the Related Art
Distribution of a power supply voltage and a reference voltage to an integrated circuit chip is a key part of the chip wiring layout design. Voltages must be distributed to all parts of the chip within strict voltage drop tolerances. Capacitance between the electrodes supplying the power and reference voltages can also be an important consideration.
U.S. Pat. No. 6,025,616 to Nguyen et al. describes a power distribution system for a semiconductor die which includes bonding pads located adjacent to and connected to power busses with connections to the bonding pads providing a parallel path for current.
U.S. Pat. No. 5,949,098 to Mori describes a semiconductor integrated circuit having a power wiring layer and a ground wiring layer with an insulating layer between the power and ground layers.
U.S. Pat. No. 5,313,079 to Brasen et al. describes gate arrays having functional blocks with flexible power routing.
U.S. Pat. No. 5,517,042 to Kitamura describes a semiconductor device having first and second device regions, a first power supply region, and a second power supply region.